Partial sums generation architecture for successive cancellation decoding of polar codes

Guillaume Berhault (1) , Camille Leroux (1) , Christophe Jego (1) , Dominique Dallet (2)

1 Conception/CSN
2 IMS - Laboratoire de l'intégration, du matériau au système

Polar codes are a new family of error correction codes for which efficient hardware architectures have to be defined for the encoder and the decoder. Polar codes are decoded using the successive cancellation decoding algorithm that includes partial sums computations. We take advantage of the recursive structure of polar codes to introduce an efficient partial sums computation unit that can also implements the encoder. The proposed architecture is synthesized for several code-lengths in 65nm ASIC technology. The area of the resulting design is reduced up to 26% and the maximum working frequency is improved by 25%.

Mots clés: application specific integrated circuits; decoding; error correction codes; ASIC technology; hardware architectures; partial sums generation architecture; polar codes; recursive structure; size 65 nm; successive cancellation decoding; FEC; hardware architecture

Domaines: Electronique

Guillaume Berhault, Camille Leroux, Christophe Jego, Dominique Dallet. Partial sums generation architecture for successive cancellation decoding of polar codes. Signal Processing Systems (SiPS), 2013 IEEE Workshop on, Oct 2013, Taipei, Taiwan. pp.407-412, ⟨10.1109/SiPS.2013.6674541⟩. ⟨hal-00955730⟩