A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers. - Archive ouverte HAL Accéder directement au contenu
Article Dans Une Revue Journal of Low Power Electronics Année : 2013

A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers.

Résumé

This paper addresses the problem of multiplication with large operand sizes (N≥32). We propose a new recursive recoding algorithm that shortens the critical path of the multiplier and reduces the hardware complexity of partial-product-generators as well. The new recoding algorithm provides an optimal space/time partitioning of the multiplier architecture for any size N of the operands. As a result, the critical path is drastically reduced to 33 N / 2 - 3 with no area overhead in comparison to modified Booth algorithm that shows a critical path of N/2 in adder stages. For instance, only 7 adder stages are needed for a 64-bit two's complement multiplier. Confronted to reference algorithms for N=64, important gain ratios of 1.62, 1.71, 2.64 are obtained in terms of multiply-time, energy consumption per multiply- operation, and total gate count, respectively.
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Dates et versions

hal-00872326 , version 1 (11-10-2013)

Identifiants

  • HAL Id : hal-00872326 , version 1

Citer

Abdelkrim K. Oudjida, Nicolas Chaillet, Mohamed L. Berrandjia, Ahmed Liacha. A New High Radix-2r (r ≥ 8) Multibit Recoding Algorithm for Large Operand Size (N ≥ 32) Multipliers.. Journal of Low Power Electronics, 2013, 9, pp.50-62. ⟨hal-00872326⟩
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