High-Speed and Low-Power PID structures for embedded applications.

Abdelkrim K. Oudjida (1) , Nicolas Chaillet (2) , Ahmed Liacha (1) , Mustapha Hamerlain (1) , Mohamed L. Berrandjia (1)

1 CDTA - Centre de Développement des Technologies Avancées
2 FEMTO-ST - Franche-Comté Électronique Mécanique, Thermique et Optique - Sciences et Technologies (UMR 6174)

In embedded control applications, control-rate and energy-consumption are two critical design issues. This paper presents a series of high-speed and low-power finite-word-length PID controllers based on a new recursive multiplication algorithm. Compared to published results into the same conditions, savings of 431% and 20% are respectively obtained in terms of control-rate and dynamic power consumption. In addition, the new multiplication algorithm generates scalable PID structures that can be tailored to the desired performance and power budget. All PIDs are implemented at RTL level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants: set-point word-length and latency.

Domaines: Micro et nanotechnologies/Microélectronique

Abdelkrim K. Oudjida, Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain, Mohamed L. Berrandjia. High-Speed and Low-Power PID structures for embedded applications.. 21th International Workshop on Power and Timing Modeling, Optimization and Simultation, PATMOS'11., Jan 2011, Spain. pp.257-266. ⟨hal-00872323⟩