HIGH-SPEED CONFLICT-FREE LAYERED LDPC DECODER FOR THE DVB-S2, -T2 AND -C2 STANDARDS - Archive ouverte HAL Accéder directement au contenu
Communication Dans Un Congrès Année : 2013

HIGH-SPEED CONFLICT-FREE LAYERED LDPC DECODER FOR THE DVB-S2, -T2 AND -C2 STANDARDS

Résumé

Layered decoding is known to provide efficient and highthroughput implementation of LDPC decoders. However, the implementation of layered architecture is not always straightforward because of memory update conflicts in the a posteriori information memory. In this paper, we focus our attention on a particular type of conflict that is due to multiple-diagonal sub-matrices in the DVB-S2, -T2 and -C2 parity-check matrices. We propose an original solution that combines repetition of the concerned layers and the write disable of the a posteriori information memory. The implementation of this solution on an FPGA-based LDPC decoder led to an average air throughput of 200 Mbit/s with a parallelism of 45 and a clock frequency of 300 MHz. Increasing the parallelism to 120 led to an average air throughput of 720 Mbit/s with a clock frequency of 400 MHz on CMOS technology.
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Dates et versions

hal-00848822 , version 1 (29-07-2013)

Identifiants

  • HAL Id : hal-00848822 , version 1

Citer

Cédric Marchand, Laura Conde-Canencia, Emmanuel Boutillon. HIGH-SPEED CONFLICT-FREE LAYERED LDPC DECODER FOR THE DVB-S2, -T2 AND -C2 STANDARDS. 2013 IEEE Workshop on SIgnal Processing Systems (SISP'2013), Oct 2013, France. pp.1-6. ⟨hal-00848822⟩
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