Development of semiconductor tracking: The future linear collider case
Résumé
An active R&D on silicon tracking for the linear collider, SiLC, is pursued since several years to develop the new generation of large area silicon trackers for the future linear collider(s). The R&D objectives on new sensors, new front end processing of the signal, and the related mechanical and integration challenges for building such large detectors within the proposed detector concepts are described. Synergies and differences with the LHC construction and upgrades are explained. The differences between the linear collider projects, namely the international linear collider, ILC, and the compact linear collider, CLIC, are discussed as well. Two final objectives are presented for the construction of this important sub-detector for the future linear collider experiments: a relatively short term design based on micro-strips combined or not with a gaseous central tracker and a longer term design based on an all-pixel tracker.The R&D objectives on sensors include single sided micro-strips as baseline for the shorter term with the strips from large wafers (at least 6 in), 200 μm thick, 50 μm pitch and the edgeless and alignment friendly options. This work is conducted by SiLC in collaboration with three technical research centers in Italy, Finland, and Spain and HPK. SiLC is studied as well, using advanced Si sensor technologies for higher granularity trackers especially short strips and pixels all based on 3D technology. New Deep Sub-Micron CMOS mix mode (analog and digital) FE and readout electronics are developed to fully process the detector signals currently adapted to the ILC cycle. It is a high-level processing and a fully programmable ASIC; highly fault tolerant. In its latest version, handling 128 channels will equip these next coming years larger size silicon tracking prototypes at test beams. Connection of the FEE chip on the silicon detector especially in the strip case is a major issue. Very preliminary results with inline pitch adapter based on wiring were just achieved. Bump-bonding or 3D vertical interconnect is the other SiLC R&D objective. The goal is to simplify the overall architecture and decrease the material budget of these devices. Three tracking concepts are briefly discussed, two of which are part of the ILC Letter of Intent of the ILD and SiD detector concepts. These last years, SiLC successfully performed beam tests to experience and test these R&D lines.