Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs

Jani Boutellier (1) , Olli Silven (1) , Mickaël Raulet (2)

1 MVG - Machine Vision Group
2 IETR - Institut d'Électronique et des Technologies du numéRique

The RVC-CAL dataflow language has recently become standardized through its use as the official language of Reconfigurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.

Mots clés: C language; FPGA; HDL synthesis; MPEG-4 simple profile video decoder; RVC-CAL dataflow language; RVC-CAL dataflow programs; TTA processor automatic synthesis; VHDL; co-design toolset; heterogeneous multiprocessor networks; instruction processors; reconfigurable video coding; transport triggered architecture; field programmable gate arrays; hardware description languages; multiprocessing systems; parallel languages; video coding

Domaines: Systèmes embarqués

Jani Boutellier, Olli Silven, Mickaël Raulet. Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs. Signal Processing Systems (SiPS), 2011 IEEE Workshop on, Oct 2011, Beyrouth, Lebanon. pp.25 -30, ⟨10.1109/SiPS.2011.6088944⟩. ⟨hal-00717332⟩