Efficient multicore scheduling of dataflow process networks

Hervé Yviquel (1, 2) , Emmanuel Casseau (1) , Matthieu Wipliez (2) , Mickaël Raulet (2)

1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
2 IETR - Institut d'Electronique et de Télécommunications de Rennes

Although multi-core processors are now available everywhere, few applications are able to truly exploit their multiprocessing capabilities. Dataflow programming attempts to solve this problem by expressing explicit parallelism within an application. In this paper, we describe two scheduling strategies for executing a dataflow program on a single-core processor. We also describe an extension of these strategies on multi-core architectures using distributed schedulers and lock-free communications. We show the efficiency of these scheduling strategies on MPEG-4 Simple Profile and MPEG-4 Advanced Video Coding decoders.

Mots clés: Dataflow computing; Multicore processing; Scheduling algorithm; Distributed algorithm; Lock-free multithreading

Domaines: Traitement du signal et de l'image [eess.SP]; Traitement du signal et de l'image [eess.SP]; Algorithme et structure de données [cs.DS]

Hervé Yviquel, Emmanuel Casseau, Matthieu Wipliez, Mickaël Raulet. Efficient multicore scheduling of dataflow process networks. IEEE Workshop on Signal Processing Systems (SiPS), Oct 2011, Beyrouth, Lebanon. pp.198 - 203, ⟨10.1109/SiPS.2011.6088974⟩. ⟨hal-00687750⟩