Construction and Evaluation of the Susceptibility Model of an Integrated Phase-Locked Loop

Alexandre Boyer (1) , Sonia Ben Dhia (1) , Christophe Lemoine (2) , Bertrand Vrignon (3)

1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
2 INSA Toulouse - Institut National des Sciences Appliquées - Toulouse
3 Freescale Semiconductor

Developing integrated circuit immunity models has become one of the major concerns of integrated circuits suppliers to predict whether a chip will pass susceptibility tests before fabrication and avoid redesign process. This paper presents the development process of the susceptibility model an integrated phase-locked loop to harmonic disturbances up to 1 GHz. The model construction is based on basic circuit information and S parameter measurements. An evaluation of the model accuracy is ensured by the characterization of internal voltage fluctuations with an on-chip sensor.

Mots clés: susceptibility; integrated circuit; phase-locked loop; on-chip measurement; modeling

Domaines: Electronique

Alexandre Boyer, Sonia Ben Dhia, Christophe Lemoine, Bertrand Vrignon. Construction and Evaluation of the Susceptibility Model of an Integrated Phase-Locked Loop. 8th Workshop on Electromagnetic Compatibility of Itnegrated Circuits, Nov 2011, Dubrovnik, Croatia. pp.7. ⟨hal-00669716⟩