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| HAL : hal-00665247, version 1 |
| Fiche détaillée |  Récupérer au format |
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| 17th Workshop on Synthesis And System Integration of Mixed Information Technologies, Beppu : Japon (2012) |
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| 16PE 3D-MESH NOC Based 3D Multicore Design and Implementation |
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| Mohammad Jabbar 1Dominique Houzet 1 |
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| (09/03/2012) |
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| In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC . The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D. |
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| 1 : | Grenoble Images Parole Signal Automatique (GIPSA-lab) |
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CNRS : UMR5216 – Université Joseph Fourier - Grenoble I – Université Pierre-Mendès-France - Grenoble II – Université Stendhal - Grenoble III – Institut Polytechnique de Grenoble - Grenoble Institute of Technology |
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| 2 : | Unité d'Électronique et d'informatique (UEI) |
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ENSTA ParisTech |
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| AGPIG |
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| Domaine | : | Sciences de l'ingénieur/Electronique |
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| 3D – multicore – mesh – noc – tezzaron |
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| hal-00665247, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00665247 | |
| oai:hal.archives-ouvertes.fr:hal-00665247 | |
| Contributeur : Dominique Houzet | |
| Soumis le : Mercredi 1 Février 2012, 14:51:48 | |
| Dernière modification le : Jeudi 16 Février 2012, 16:42:11 | |
