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| HAL : hal-00665217, version 1 |
| Fiche détaillée |  Récupérer au format |
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| IEEE International 3D System Integration Conference (3DIC), Osaka : Japon (2012) |
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| 3D Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology |
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| Mohammad Jabbar 1Dominique Houzet 1 |
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| (02/02/2012) |
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| In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D. |
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| 1 : | Grenoble Images Parole Signal Automatique (GIPSA-lab) |
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CNRS : UMR5216 – Université Joseph Fourier - Grenoble I – Université Pierre-Mendès-France - Grenoble II – Université Stendhal - Grenoble III – Institut Polytechnique de Grenoble - Grenoble Institute of Technology |
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| 2 : | Unité d'Électronique et d'informatique (UEI) |
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ENSTA ParisTech |
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| AGPIG |
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| Domaine | : | Sciences de l'ingénieur/Electronique |
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| Liste des fichiers attachés à ce document : | |||||
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| hal-00665217, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00665217 | |
| oai:hal.archives-ouvertes.fr:hal-00665217 | |
| Contributeur : Dominique Houzet | |
| Soumis le : Mercredi 1 Février 2012, 14:11:39 | |
| Dernière modification le : Jeudi 16 Février 2012, 16:51:33 | |
