ULP Variability-insensitive SRAM design in sub-32nm UTBB FDSOI CMOS

Adam Makosiej (1) , Andrei Vladimirescu (2) , Olivier Thomas (3) , Amara Amara (1)

1 MINARC
2 MINARC
3 CEA-LETI - Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information

This paper describes a design approach based on optimization of embedded SRAMs that takes advantage of an Ultra-Thin Body and Box (UTBB) Fully-Depleted (FD) SOI CMOS process. Optimization is performed on an analytical model including statistical variations for Static Noise Margin (SNM) of CMOS SRAMs operating in subthreshold. Distributions of retention and read SNM are derived as a function of VTN and VTP. Improvements of up to 2x of the retention- and read-mode SNM µ/σ are obtained by optimizing the VTN/VTP ratio with back bias.

Domaines: Electronique

Adam Makosiej, Andrei Vladimirescu, Olivier Thomas, Amara Amara. ULP Variability-insensitive SRAM design in sub-32nm UTBB FDSOI CMOS. EUROSOI 2011, Jan 2011, Granada, Spain. pp.35-36. ⟨hal-00643894⟩