Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments

Christophe Krzeminski (1)

1 IEMN - Institut d’Électronique, de Microélectronique et de Nanotechnologie - UMR 8520

Strain engineering is the main technological booster used by semiconductor companies for the 65 and 45nm technology nodes to improve the channel mobility and the electrical performance of logic devices. For 32 and 22nm nodes, intense research work focuses on the integration and optimisation of these different techniques by cumulating the effects of different stressors. To estimate the level and the distribution of the stress field generated in the transistor channel by such multiple processing steps is a complex issue. Process simulation has a role to play in order to face the many challenges in term of scalability, yield and design. The objective of this paper is first to evaluate the stress distribution generated by the two most usual processing steps: Contact Etch Stop Liner (CESL) and embedded SiGe Stressors (eSiGe). Next, the final stress field in nanoscale device resulting of these intentionally but also parasitic sources are evaluated. Process simulations have been able to quantify the global trend observed in these stressors in relatively close correlation with experiment.

Mots clés: Stress engineering; Contact Etch Stop Liner; SiGe stressor; Finite elements simulation; Strain measurement; CBED; Holography

Domaines: Micro et nanotechnologies/Microélectronique

Christophe Krzeminski. Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments. Journal of vaccum Science and Technology B, 2012, 30 (2), pp.022203-1. ⟨10.1116/1.3683079⟩. ⟨hal-00624131⟩