| The shrinking of processing technology in the deep submicron domain aggravates the imbalance between gate delays and wire delays. While a Network-on-Chip systematically tackles this physical issue by differentiating between local and global interconnects, 3D-Integration by folding the die into multiple layers and using short vertical links instead of long horizontal interconnects, leads to a considerable reduction in the length and the number of long global wires. This chapter elaborates on the strategic exploitation of these two key technologies, where the use of the third dimension in the design of the integrated networks provides a major improvement in the network performance. It makes a case for using asynchronous circuits to implement 3D-NoCs. We claim that asynchronous logic allows benefiting from serialized vertical link leading to the definition of innovative architectures which can address some critical issues of 3D integrated circuits using Through-Silicon-Vias. This allows complying with the cost-efficiency trade-off of the 3D-Integration paradigm. |
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