Relecture de bitstream appliquée à la relocation de tâches matérielles dans les SoC reconfigurables

Frederic de Melo (1) , Laurent Gantel (1, 2) , Romain Sachaux (1)

1 ETIS - UMR 8051 - Equipes Traitement de l'Information et Systèmes
2 Thales Research and Technology [Palaiseau]

Nowadays FPGAs allows us to integrate at the same time hardware and software tasks, with the addition of one or several processors. These new architectures open the way to the exploration of heterogeneous systems where the hardware and software tasks have to possess the same properties of preemption face to face of a real-time operating system of a new kind. This article presents a methodology allowing to make the readback of the bitstream of a hardware task to perform its relocation on Xilinx Virtex-5's architecture.

Mots clés: readback; bitstream; virtex5; reconfigurable; frame

Domaines: Architectures Matérielles [cs.AR]

Frederic de Melo, Laurent Gantel, Romain Sachaux. Relecture de bitstream appliquée à la relocation de tâches matérielles dans les SoC reconfigurables. GDR SOCSIP, Jun 2010, Cergy-Pontoise, France. ⟨hal-00551374⟩