Automatic Method For Efficient Hardware Implementation From RVC-CAL Dataflow: A LAR Coder baseline Case Study

Khaled Jerbi (1, 2) , Matthieu Wipliez (2) , Mickaël Raulet (3) , Olivier Déforges (2) , Marie Babel (2) , Mohamed Abid (1)

1 CEM Lab - ENIS - Département de Génie Électrique de Sfax [ENIS]
2 IETR - Institut d'Electronique et de Télécommunications de Rennes
3 IETR - Institut d'Électronique et des Technologies du numéRique

Implementing an algorithm to hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated to a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because the designer must take care of low-level details, and write test benches to test the implementation's behavior. This paper presents a global design method going from high level description to implementation. The first step consists of the description of an algorithm as a dataflow program with the RVC-CAL language. Next step is the functional verification of this description using a software framework. The final step consists of an automatic generation of an efficient hardware implementation from the dataflow program. The objective was to spend the most part of the conception time in an open source software platform. We used this method to quickly prototype and generate hardware implementation of a baseline part of the LAR coder, from an RVC-CAL description.

Domains: Signal and Image processing; Hardware Architecture [cs.AR]; Signal and Image Processing

Khaled Jerbi, Matthieu Wipliez, Mickaël Raulet, Olivier Déforges, Marie Babel, et al.. Automatic Method For Efficient Hardware Implementation From RVC-CAL Dataflow: A LAR Coder baseline Case Study. "Section E: Consumer Electronics" of the Journal of Convergence, 2010, pp.85-92. ⟨hal-00546742⟩