Parallel Application Sampling in MPSoC Simulation

Melhem Tawk (1) , Khaled Ibrahim (2) , Smail Niar (1)

1 LAMIH - Laboratoire d'Automatique, de Mécanique et d'Informatique industrielles et Humaines - UMR 8201
2 LBNL - Lawrence Berkeley National Laboratory [Berkeley]

Multi-processor system-on-chip (MPSoC) simulators are many orders of magnitude slower than the hardware they simulate due to increasing architectural complexity. In this paper, we propose a new application sampling technique to accelerate the simulation of MPSoC design space exploration (DSE). The proposed technique dynamically combines simultaneously executed phases, thus generating a sampling unit. This technique accelerates the simulation by allowing the repeated combinations of parallel phases to be skipped. A complementary technique, called cluster synthesis, is also proposed to improve the simulation acceleration when the number of possible phase combinations increases. Our experimental results show that this technique can accelerate the simulation up to a factor of 800 with a relatively small estimation error.

Mots clés: Embedded systems; MPSoC; Simulation; Application Sampling

Domaines: Systèmes embarqués; Architectures Matérielles [cs.AR]

Melhem Tawk, Khaled Ibrahim, Smail Niar. Parallel Application Sampling in MPSoC Simulation. International Journal on Design Automation for Embedded Systems, 2010, Volume 14 / 2010, pp.1. ⟨10.1007/s10617-010-9064-0⟩. ⟨hal-00522847⟩