A Current Shaping Methodology for Low EMI Asynchronous Circuits

D. Panyasak (1) , Gilles Sicard (1) , Marc Renaudin (1, 2)

1 TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés
2 Tiempo SAS [Montbonnot Saint Martin]

The paper describes a design methodology for reducing current peaks in asynchronous digital circuits. Two existing methods influence this methodology, which deals with circuits at the architecture level. It spreads the current activity inside the circuit by controlling communication delays and events scheduling. A 4-taps FIR filter, synthesized in a 0.18μm CMOS technology, proves the methodology efficiency obtaining 20% peak current reduction and no significant area overhead before layout.

Mots clés: EMC; IC; emission; immunity; susceptibility; modelling; IEC; integrated circuit; electromagnetic compatibility

Domaines: Micro et nanotechnologies/Microélectronique

D. Panyasak, Gilles Sicard, Marc Renaudin. A Current Shaping Methodology for Low EMI Asynchronous Circuits. 3rd International Workshop on Electromagnetic Compatibility of Integrated Circuits, Nov 2002, Toulouse, France. pp. 43-48. ⟨hal-00517781⟩