HAL: hal-00509485, version 1

DOI: 10.4236/cs.2010.11004

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Circuits and Systems 1, 1 (2010) pp 18-29

FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Hassen Loukil 1, Imen Werda 1, Nouri Masmoudi 1, Ahmed Ben Atitallah 1, 2, Patrice Kadionik 2

(2010-07-01)

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II de-velopment board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

1:	Laboratory of Electronics and Information Technology (LETI)
	Université de Sfax
2:	Laboratoire de l'intégration, du matériau au système (IMS)
	CNRS : UMR5218 – Université Sciences et Technologies - Bordeaux I – Ecole Nationale Supérieure d'Electronique, Informatique et Radiocommunications de Bordeaux – École Nationale Supérieure de Chimie et de Physique de Bordeaux

Subject

:

Engineering Sciences/Micro and nanotechnologies/Microelectronics

Keyword(s): Nios – H.264 – FPGA – Intra 16 × 16 – NIOS-II – SOPC Design

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From: Patrice Kadionik <>

Submitted on: Thursday, 12 August 2010 17:18:42

Updated on: Sunday, 5 September 2010 18:48:44