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| HAL : hal-00509485, version 1 |
| DOI : 10.4236/cs.2010.11004 |
| Fiche détaillée |  Récupérer au format |
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| Circuits and Systems 1, 1 (2010) pp 18-29 |
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| FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder |
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| Hassen Loukil 1Imen Werda 1 |
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| (01/07/2010) |
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| In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II de-velopment board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work. |
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| 1 : | Laboratory of Electronics and Information Technology (LETI) |
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Université de Sfax |
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| 2 : | Laboratoire de l'intégration, du matériau au système (IMS) |
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CNRS : UMR5218 – Université Sciences et Technologies - Bordeaux I – Institut Polytechnique de Bordeaux |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| Nios – H.264 – FPGA – Intra 16 × 16 – NIOS-II – SOPC Design |
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| hal-00509485, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00509485 | |
| oai:hal.archives-ouvertes.fr:hal-00509485 | |
| Contributeur : Patrice Kadionik | |
| Soumis le : Jeudi 12 Août 2010, 17:18:42 | |
| Dernière modification le : Dimanche 5 Septembre 2010, 18:48:44 | |
