Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.

Rola Kassem (1) , Mikaël Briday (1) , Jean-Luc Béchennec (1) , Yvon Trinquet (1) , Guillaume Savaton (2)

1 IRCCyN - Institut de Recherche en Communications et en Cybernétique de Nantes
2 ESEO-Tech

Hardware simulation is an important part of the design of embedded and/or real-time systems. It can be used to compute the Worst Case Execution Time (WCET) and to provide a mean to run software when final hardware is not yet available. Building a simulator is a long and difficult task, especially when the architecture of processor is complex. This task can be alleviated by using a Hardware Architecture Description Language and generating the simulator. In this article we focus on a technique to generate an automata based simulator from the description of the pipeline. The description is transformed into an automaton and a set of resources which, in turn, are transformed into a simulator. The goal is to obtain a cycle-accurate simulator to verify timing characteristics of embedded real-time systems. An experiment compares an Instruction Set Simulator with and without the automaton based cycle-accurate simulator.

Domaines: Modélisation et simulation; Systèmes embarqués; Architectures Matérielles [cs.AR]

Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton. Simulator Generation Using an Automaton Based Pipeline Model for Timing Analysis.. International Multiconference on Computer Science and Information Technology (IMCSIT), International Workshop on Real Time Software (RTS'08)., Oct 2008, Wisla, Poland. pp.657-664. ⟨hal-00486839⟩