HAL: hal-00484704, version 1

DOI: 10.1016/j.aeue.2010.02.012

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AEÜ - International Journal of Electronics and Communications / Archiv für Elektronik und Übertragungstechnik 65, 3 (2010) pp 250-257

FPGA implementation of vector directional distance filter based on HW/SW environment validation

Anis Boudabous 1, Ahmed Ben Atitallah 1, 2, Lazhar Khriji 3, Patrice Kadionik 2, Nouri Masmoudi 1

(2010-05-13)

In this paper a new FPGA implementation approach of vector directional distance filter (VDDF) using HW/SW solution is presented. The challenges of our solution include ease of implementation, good accuracy and relatively high speed. We use approximations to solve hardware limitations. HW/SW solution uses Nios-II FPGA development board. Experimental results using a number of color images show that the approximated VDDF achieves an excellent balance between computational speed and filtering quality. Moreover, the efficient design processes at 110 MHz system clock and gives a good execution time compared to the software based solution.

1:	Laboratory of Electronics and Information Technology (LETI)
	Université de Sfax
2:	Laboratoire de l'intégration, du matériau au système (IMS)
	CNRS : UMR5218 – Université Sciences et Technologies - Bordeaux I – Ecole Nationale Supérieure d'Electronique, Informatique et Radiocommunications de Bordeaux – École Nationale Supérieure de Chimie et de Physique de Bordeaux
3:	Dept. of Electrical and Computer Engineering
	Sultan Qaboos University

Subject

:

Engineering Sciences/Micro and nanotechnologies/Microelectronics

Keyword(s): Nonlinear filter – Color image – FPGA implementation – Hardware acceleration

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From: Patrice Kadionik <>

Submitted on: Tuesday, 18 May 2010 19:44:48

Updated on: Sunday, 28 August 2011 01:50:20