A 10 000 fps CMOS Sensor With Massively Parallel Image Processing

Jérôme Dubois (1) , Dominique Ginhac (2) , Michel Paindavoine (2) , Barthélémy Heyrman (2)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 Le2i - Laboratoire Electronique, Informatique et Image [UMR6306]

A high-speed analog VLSI image acquisition and preprocessing system has been designed and fabricated in a 0.35 standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. Measured results show that the proposed sensor successfully captures raw images up to 10 000 frames per second and runs low-level image processing at a frame rate of 2000 to 5000 frames per second.

Mots clés: CMOS image sensor; parallel architecture; high- speed image processing; analog arithmetic unit.; analog arithmetic unit

Domaines: Traitement du signal et de l'image [eess.SP]; Electronique; Micro et nanotechnologies/Microélectronique; Traitement du signal et de l'image [eess.SP]

Jérôme Dubois, Dominique Ginhac, Michel Paindavoine, Barthélémy Heyrman. A 10 000 fps CMOS Sensor With Massively Parallel Image Processing. IEEE Journal of Solid-State Circuits, 2008, 43 (3), pp.706-717. ⟨10.1109/JSSC.2007.916618⟩. ⟨hal-00482751⟩