Simulation-based validation of VHDL descriptions using constraints logic programming

Christophe Paoli (1) , Marie Laure Nivet (1) , Fabrice Bernardi (1) , Laurent Capocchi (1)

1 SPE - Sciences pour l'environnement

This paper presents a simulation based validation approach for test vectors generation. We suggest to borrow techniques used successfully in the software testing and constraints logic programming areas. Our methodology is based on the three following steps: VHDL code modeling and analysis, constraints-based stimuli generation and test sequences generation.

Domaines: Electronique

Christophe Paoli, Marie Laure Nivet, Fabrice Bernardi, Laurent Capocchi. Simulation-based validation of VHDL descriptions using constraints logic programming. IEEE Workshop on RTL and High Level Testing, Nov 2004, Osaka, Japan. pp.S2.3. ⟨hal-00440834⟩