A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems

Maxime Pelcat (1) , Jean François Nezan (1) , Jonathan Piat (2) , Jerome Croizer (2) , Slaheddine Aridhi (3)

1 IETR - Institut d'Électronique et des Technologies du numéRique
2 IETR - Institut d'Electronique et de Télécommunications de Rennes
3 CIV Texas Instruments

Modern embedded systems tend to consist of multiple processors like multicore DSP (Digital Signal Processor) or MPSoC (Multiprocessor System-on-Chip). Static task scheduling for rapid prototyping of parallel embedded systems is different from the dynamic monocore scheduling problem. The communication between cores has a very high impact on the scheduling and the resulting use of hardware resources. Taking into account communication costs and competition can increase excessively the time spent in the prototyping. The System-Level Architecture Model proposed in this paper aims to provide simple system-level descriptions of architectures. The model is expressive enough to enable simulation of modern architecture behaviors. It also reduces the complexity of static mapping-scheduling by precalculating routes between elements.

Domaines: Multimédia [cs.MM]; Calcul parallèle, distribué et partagé [cs.DC]; Systèmes embarqués

Maxime Pelcat, Jean François Nezan, Jonathan Piat, Jerome Croizer, Slaheddine Aridhi. A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems. Conference on Design and Architectures for Signal and Image Processing (DASIP) 2009, Sep 2009, nice, France. 8 p. ⟨hal-00429397⟩