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| HAL : hal-00378128, version 1 |
| DOI : 10.1109/VTS.2008.15 |
| Fiche détaillée |  Récupérer au format |
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| IEEE VLSI Test Symposium (VTS'08), San Diego, California : États-Unis (2008) |
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| Low-Cost Highly-Robust Hardened Storage Cells Using Blocking Feedback Transistors |
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| M. Nicolaidis 1R. Perez Ribas 2 |
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| (2008) |
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| CMOS nanometric technologies are increasingly sensitive to soft errors, including SEUs affecting storage cells and SETs initiated in the combinational logic, and eventually captured by some latches or flip- flops. SEUs affecting latches or flip-flops are by far the largest soft error rate (SER) contributor in logic. Thus, developing cost-efficient hardened storage cells to cope with SEUs in latches and flip-flops (but also in some memories difficult to protect by ECC ) is of increasing importance. This paper proposes a new principle for designing low-cost highly robust storage cells and several transistor level implementations. |
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| 1 : | iROc Technologies (IROC TECHNOLOGIES) |
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Cadence Connection – EDA Consortium – FSA – Cubic Micro |
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| 2 : | Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) |
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CNRS : UMR5159 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| hardened-register – low-cost |
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| hal-00378128, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00378128 | |
| oai:hal.archives-ouvertes.fr:hal-00378128 | |
| Contributeur : Lucie Torella | |
| Soumis le : Jeudi 23 Avril 2009, 15:40:47 | |
| Dernière modification le : Jeudi 23 Avril 2009, 15:40:47 | |
