Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems

Pierre Bomel (1) , Jean-Philippe Diguet (1) , Guy Gogniat (2) , Jeremie Crenne (2)

1 Lab-STICC_UBS_CACS_MOCS
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192)

In this paper we present a hierarchy of bitstreams repositories for FPGA-based networked and partially reconfigurable systems. These systems target embedded systems with very scarce hardware resources taking advantage of dynamic, specific and optimized architectures. Based on FPGA integrated circuits, they require a single FPGA with a network controller and less external memories to store reconfiguration software, bitstreams and buffer pools used by today's standard communication protocols. Our measures, based on a real implementation, show that our repository hierarchy is functional and can download bitstreams with a reconfiguration speed ten times faster than known solutions.

Mots clés: FPGA; partial reconfiguration; communication protocol; local area network; bistream repository

Domaines: Electronique

Pierre Bomel, Jean-Philippe Diguet, Guy Gogniat, Jeremie Crenne. Bitstreams Repository Hierarchy for FPGA Partially Reconfigurable Systems. 2008. ⟨hal-00369078⟩