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| HAL : hal-00345737, version 1 |
| Fiche détaillée |  Récupérer au format |
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| International Workshop on Power and Timing Modeling, Optimization and Simulation. PATMOS 2008, Lisbonne : Portugal (2008) |
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| Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses |
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| Antoine Courtay 1, 2Johann Laurent 2 |
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| (10/09/2008) |
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| Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data coding for interconnect power and timing optimization has been introduced. In today's SoCs these techniques are not efficient anymore due to their codec complexity or to their unrealistic experimentations. Based on some realistic observations on interconnect delay and power estimation, the spatial switching technique is proposed. It allows the reduction of delay and power consumption (including extra power consumption due to codecs) for on-chip buses. The concept of the technique is to detect all cross-transitions on adjacent wires and to decide if the adjacent wires are exchanged or not. Results show the spatial switching efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 5-mm bus and more if buses are longer. |
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| 1 : | CAIRN (INRIA - IRISA) |
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INRIA – CNRS : UMR6074 – École normale supérieure de Cachan - ENS Cachan – Institut National des Sciences Appliquées (INSA) - Rennes – Université de Rennes 1 |
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| 2 : | Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (Lab-STICC) |
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CNRS : UMR3192 – Université de Bretagne Occidentale (UBO) – Université de Bretagne Sud – Institut Mines-Télécom – Télécom Bretagne – PRES Université Européenne de Bretagne [UEB] – Institut Supérieur des Sciences et Technologies de Brest (ISSTB) |
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| Lab-STICC_UBS_CACS_MOCS Lab-STICC_UBS_CACS_CS,Lab-STICC_UBS_CACS_MOCS |
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| Domaine | : | Sciences de l'ingénieur/Micro et nanotechnologies/Microélectronique |
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| Interconnect – Power Consumption – Performance optimization |
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| hal-00345737, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00345737 | |
| oai:hal.archives-ouvertes.fr:hal-00345737 | |
| Contributeur : Antoine Courtay | |
| Soumis le : Mardi 9 Décembre 2008, 17:30:24 | |
| Dernière modification le : Mardi 9 Février 2010, 16:08:54 | |
