μSPIDER CAD TOOL: CASE STUDY OF NOC IP GENERATION FOR FPGA

Samuel Evain (1) , Rachid Dafali (2) , Jean-Philippe Diguet (3) , Yvan Eustache (2) , Emmanuel Juin (2)

1 LIST (CEA) - Laboratoire d'Intégration des Systèmes et des Technologies
2 LESTER - Laboratoire d'Electronique des Systèmes TEmps Réel
3 Lab-STICC_UBS_CACS_MOCS

This paper introduces the μSpider CAD tool for NoC design under latency and bandwidth constraints and describes the different steps of the associated design flow. We show how the tool can be used to automatically generate a NOC IP compliant with Xilinx EDK tool. We present synthesis results and a real implementation of a video application based on a multi-processor architecture. Finally we conclude about research to be done at application/OS levels above current work to achieve a complete and efficient implementation of a multi-processor embedded system.

Mots clés: NoC; CAD tool; design flow; microSpider

Domaines: Architectures Matérielles [cs.AR]

Samuel Evain, Rachid Dafali, Jean-Philippe Diguet, Yvan Eustache, Emmanuel Juin. μSPIDER CAD TOOL: CASE STUDY OF NOC IP GENERATION FOR FPGA. Dasip07, Nov 2007, France. ⟨hal-00338244⟩