HAL: hal-00311431, version 1

DOI: 10.1109/FDTC.2008.18

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FDTC, Washington, DC : United States (2008)

Silicon-level Solutions to Counteract Passive and Active Attacks

Sylvain Guilley 1, Laurent Sauvage 1, Jean-Luc Danger 1, Nidhal Selmane 1, Renaud Pacalet 1

For the MARS (ACI SI 2004), CALISSON (FUI #4), Institut TELECOM (Trusted Computing Platform) collaboration(s)

(2008-08-10)

This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published ``implementation-level'' attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about ``dual counter-measures'', that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS. We highlight some research directions towards dependable and cost-effective dual counter-measures.

1:	Laboratoire traitement et communication de l'information (LTCI)
	CNRS : UMR5141 – Institut Télécom – Télécom ParisTech

Subject

:

Computer Science/Cryptography and Security

Keyword(s): side-channel attacks (SCA) – differential power analysis (DPA) – SecMat ASIC family – dual-rail with precharge logic (DPL) – SecLib DPL style – differential fault attack (DFA) – FPGA as evaluation platforms – attacks mitigation techniques – dual DPA-DFA counter-measures.

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From: Sylvain Guilley <>

Submitted on: Sunday, 17 August 2008 13:09:42

Updated on: Sunday, 7 December 2008 13:33:06