Silicon-level Solutions to Counteract Passive and Active Attacks

Sylvain Guilley (1) , Laurent Sauvage (1) , Jean-Luc Danger (1) , Nidhal Selmane (1) , Renaud Pacalet (1)

1 LTCI - Laboratoire Traitement et Communication de l'Information

This article presents a family of cryptographic ASICs, called SecMat, designed in CMOS 130 nanometer technology by the authors with the help of STMicroelectronics. The purpose of these prototype circuits is to experience with the published ``implementation-level'' attacks (SPA, DPA, EMA, templates, DFA). We report our conclusions about the practicability of these attacks: which ones are the most simple to mount, and which ones require more skill, time, equipments, etc. The potential of FPGAs as security evaluation commodities at design time is also detailed. Then, we discuss about ``dual counter-measures'', that are meant to resist both passive and active attacks. This study started four years ago with TIMA (Grenoble), in the framework of the project MARS. We highlight some research directions towards dependable and cost-effective dual counter-measures.

Mots clés: side-channel attacks (SCA); differential power analysis (DPA); SecMat ASIC family; dual-rail with precharge logic (DPL); SecLib DPL style; dual DPA-DFA counter-measures.; differential fault attack (DFA); FPGA as evaluation platforms; attacks mitigation techniques; dual DPA-DFA counter-measures

Domaines: Cryptographie et sécurité [cs.CR]

Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet. Silicon-level Solutions to Counteract Passive and Active Attacks. FDTC, Aug 2008, Washington, DC, United States. pp.3-17, ⟨10.1109/FDTC.2008.18⟩. ⟨hal-00311431⟩