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| HAL: hal-00310999, version 1 |
| DOI: 10.1007/s10617-006-9044-6 |
| Detailed view |  Export this paper |
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| Design Automation for Embedded Systems 10, 32 (2005) 73-104 |
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| LusSy: an Open Tool for the Analysis of Systems-on-a-Chip at the Transaction Level |
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| Matthieu Moy 1Florence Maraninchi 1 |
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| (2005-09) |
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| We describe a toolbox for the analysis of Systems-on-a-chip written in SystemC at the transaction level. The tool is able to extract information from SystemC code, and to build a set of parallel automata that capture the semantics of a SystemC design, including the transaction-level specific constructs. As far as we know, this provides the first executable formal semantics of SystemC. Being implemented as a traditional compiler front-end, it is able to deal with general SystemC designs. The intermediate representation is now connected to existing formal verification tools via appropriate encodings. The toolbox is open and other tools will be used in the future. |
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| 1: | VERIMAG (VERIMAG - IMAG) |
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CNRS : UMR5104 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG) |
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| 2: | STMicroelectronics (Crolles) (ST-CROLLES) |
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STMicroelectronics |
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| Subject | : | Computer Science/Programming Languages Computer Science/Embedded Systems Computer Science/Modeling and Simulation |
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| SystemC – formal verification – lussy – pinapa – model-checking – lesar – lustre – tlm – transaction-level modeling |
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| hal-00310999, version 1 | |
| http://hal.archives-ouvertes.fr/hal-00310999 | |
| oai:hal.archives-ouvertes.fr:hal-00310999 | |
| From: Matthieu Moy | |
| Submitted on: Wednesday, 13 August 2008 00:22:19 | |
| Updated on: Wednesday, 13 August 2008 13:29:46 | |
