A secure asynchronous configurable cell: an embedded programmable logic for smartcards
Résumé
With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA (e-FPGA) co-processor are becoming a viable alternative. Within the SAFE project which aims the design of an e-FPGA, a new programmable asynchronous cell has been studied. This cell is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Nevertheless, counter-measures at the electrical level are not a sufficient protection in programmable logic architectures to be resistant to these attacks. Indeed, the place-and-route operation on the programmable logic is also crucial. Therefore dedicated back-end tools are required to ensure a high level of resistance to side-channel attacks. An appropriated mapping algorithm has been developed to meet these security requirements onto the programmable logic cell. Electrical simulations show the security enhancement provided by such a configurable cell.