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| HAL : hal-00283405, version 5 |
| Fiche détaillée |  Récupérer au format |
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| Conference on Design of Circuits and Integrated Systems, Grenoble : France (2008) |
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| Versions disponibles : | v1 (30-05-2008) | v2 (29-11-2008) | v3 (25-05-2009) | v4 (26-06-2009) | v5 (19-02-2010) |
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| Security Evaluation of a Balanced Quasi-Delay Insensitive Library (SecLib) |
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| Sylvain Guilley 1Florent Flament 1 |
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| (11/2008) |
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| This article presents a library of cells enabling the realization of constant-power cryptoprocessors, natively protected against side-channel attacks exploiting the instant power consumption. The proposed methodology uses a full-custom balanced quasi-delay insensitive (QDI) cell library, called ``SecLib''. It is suitable for a shielded routing method derived from the ``backend duplication'', using legacy CAD tools for the backend steps. The discussion is oriented towards the explicitation of topological constraints encountered in highly secure designs. We discuss the impact of intra-die technological mismatch on the security of SecLib. |
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| 1 : | Laboratoire traitement et communication de l'information (LTCI) |
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CNRS : UMR5141 – Institut Télécom – Télécom ParisTech |
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| Domaine | : | Informatique/Cryptographie et sécurité |
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| Standard cells design – power-constant logic – side-channel attacks mitigation – transistors mismatch – Monte-Carlo simulation |
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| hal-00283405, version 5 | |
| http://hal.archives-ouvertes.fr/hal-00283405 | |
| oai:hal.archives-ouvertes.fr:hal-00283405 | |
| Contributeur : Sylvain Guilley | |
| Soumis le : Vendredi 19 Février 2010, 01:49:43 | |
| Dernière modification le : Vendredi 19 Février 2010, 09:34:39 | |
