HAL : hal-00259153, version 5

DOI : 10.1109/SSIRI.2008.31

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Secure System Integration and Reliability Improvement, Yokohama : Japan (2008)

Versions disponibles :

v1 (28-02-2008)

v2 (11-03-2008)

v3 (06-08-2008)

v4 (19-08-2009)

v5 (20-11-2009)

Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs

Sylvain Guilley 1, Laurent Sauvage 1, Jean-Luc Danger 1, Tarik Graba 1, Yves Mathieu 1

(14/07/2008)

FPGAs are often considered for high-end applications that require embedded cryptography. These devices must thus be protected against physical attacks. However, unlike ASICs, in which custom and backend-level counter-measures can be devised, FPGAs offer less possibilities for a designer to implement counter-measures. We investigate in this article ``Wave Dynamic Differential Logic'' (WDDL), a logic-level counter-measure based on leakage hiding thanks to balanced dual-rail logic. First of all, we report a CAD methodology for achieving WDDL in FPGA. An experimental security evaluation of the DES encryption algorithm in WDDL shows that the usage of positive logic is mandatory to resist to straightforward attacks. Second, we discuss how to reduce the size overhead associated with WDDL. The efficiency of some synthesizers is assessed. In the case of DES, we provide with an original heuristic to obtain substitution boxes smaller than those generated automatically with legacy ASIC synthesizers.

1 :	Laboratoire traitement et communication de l'information (LTCI)
	CNRS : UMR5141 – Institut Télécom – Télécom ParisTech

Domaine

:

Informatique/Cryptographie et sécurité

Mots Clés : FPGA – security – side-channel attacks – attacks mitigation – power-constant logic – positive dual-rail logic

hal-00259153, version 5

http://hal.archives-ouvertes.fr/hal-00259153

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Contributeur : Sylvain Guilley <>

Soumis le : Vendredi 20 Novembre 2009, 01:47:34

Dernière modification le : Vendredi 20 Novembre 2009, 05:29:05