HAL : hal-00256628, version 2

DOI : 10.1109/CDC.2011.6160449

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50th IEEE Conference on Decision and Control and European Control Conference (CDC-ECC), Orlando : United States (2011)

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v1 (18-02-2008)

v2 (21-08-2012)

Optimal and Robust Saturated Control for a Clock Generator

Carolina Albea-Sanchez (  Auteur correspondant ) 1, Suzanne Lesecq 2, Diego Puschini 2

(12/12/2011)

Fine-grain Dynamic Voltage and Fre- quency Scaling (DVFS) is becoming a requirement for Globally-Asynchronous Locally-Synchronous (GALS) architectures. However, the area overhead of adding voltage and frequency control engines in each volt- age/frequency island must be taken into account to optimize the circuit. This paper focuses on the control for the frequency actuator. An optimal and robust saturated control law, with a minimum hardware implementation area is proposed for a Clock Gen- erator, taking into account the delay introduced by the sensor. This controller is designed with Lyapunov-Krasovskii theory that ensures asymptotic stability, disturbance rejection as well as system robustness with respect to delay presence and parameter uncertainties. The closed-loop system presents a regional stabilization due to the actuator saturation. An estimation of a maximum attraction domain is provided. The performance achieved with this controller are shown in simulation.

1 :	Laboratoire d'analyse et d'architecture des systèmes (LAAS)
	CNRS : UPR8001 – Université Paul Sabatier [UPS] - Toulouse III – Institut National Polytechnique de Toulouse - INPT – Institut National des Sciences Appliquées (INSA) - Toulouse
2 :	Laboratoire d'Electronique et des Technologies de l'Information (LETI)
	CEA : DRT/LETI

Domaine

:

Informatique/Automatique

Mots Clés : Robust control – optimal control – delay-time systems – Nano circuits

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Contributeur : Carolina Albea-Sanchez <>

Soumis le : Mardi 21 Août 2012, 12:43:31

Dernière modification le : Jeudi 13 Septembre 2012, 09:55:41