Choice of a high level fault model for the Optimization of Validation Test Set reused for Manufacturing Test

Yves Joannon (1) , Vincent Beroulle (1) , Chantal Robach (1) , Smail Tedjini (1) , Jean-Louis Carbonero (2)

1 LCIS - Laboratoire de Conception et d'Intégration des Systèmes
2 ST-CROLLES - STMicroelectronics [Crolles]

With the growing complexity of Wireless Systems on Chip integrating hundred-of-million transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and re-used for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipments costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

Domaines: Micro et nanotechnologies/Microélectronique; Electronique

Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonero. Choice of a high level fault model for the Optimization of Validation Test Set reused for Manufacturing Test. IMSTW'07, Jun 2007, Porto, Portugal. pp.66 - 71. ⟨hal-00250422⟩