Very Fast Chip-level Thermal Analysis

K. Nakabayashi (1) , T. Nakabayashi (2) , K. Nakajima (3)

1 Graduate School of Information Science
2 Graduate School of Humanities and Sciences
3 Dept. of Electrical and Computer Engineering

We present a new technique of VLSI chip-level thermal analysis. We extend a newly developed method of solving two dimensional Laplace equations to thermal analysis of four adjacent materials on a mother board. We implement our technique in C and compare its performance to that of a commercial CAD tool. Our experimental results show that our program runs 5.8 and 8.9 times faster while keeping smaller residuals by 5 and 1 order of magnitude, respectively.

Mots clés: Fast thermal analysis; multi-layer structre; direct linear system solver

Domaines: Science des matériaux [cond-mat.mtrl-sci]

K. Nakabayashi, T. Nakabayashi, K. Nakajima. Very Fast Chip-level Thermal Analysis. THERMINIC 2007, Sep 2007, Budapest, Hungary. pp.82-87. ⟨hal-00202539⟩