HAL : hal-00189567, version 1

DOI : 10.1109/ACSD.2006.24

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Sixth International Conference on Application of Concurrency to System Design (ACSD'06), Turku : Finland (2006)

Simulation and Verification of Asynchronous Systems by means of a Synchronous Model

Nicolas Halbwachs 1, Louis Mandel 1

ASSERT Collaboration(s)

(06/2006)

Synchrony and asynchrony are commonly opposed to each other. Now, in embedded applications, actual solutions are often situated in between, with synchronous processes composed in a partially asynchronous way. Examples of such intermediate solutions are GALS, quasi-synchronous periodic processes, deadline-driven task scheduling. . . In this paper, we illustrate the use of the synchronous paradigm to model and validate such partially asynchronous applications. We show that, through the use of sporadic activation of processes and simulation of nondeterminism by the way of auxiliary inputs, the synchronous paradigm allows a precise control of asynchrony. The approach is illustrated on a real case study, proposed in the framework of the European Integrated project "Assert".

1 :	VERIMAG (VERIMAG - IMAG)
	CNRS : UMR5104 – Université Joseph Fourier - Grenoble I – Institut National Polytechnique de Grenoble (INPG)

Équipe de recherche : SYNCHRONE

Domaine

:

Informatique/Systèmes embarqués

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Contributeur : Nicolas Halbwachs <>

Soumis le : Mercredi 21 Novembre 2007, 13:45:27

Dernière modification le : Mercredi 21 Novembre 2007, 21:50:13