A comprehensive thermal-aware power mangement system with block-level optimization in 100nm CMOS technology

W.-M. Chan (1) , H. Chiueh (1)

1 SoC Design Lab

Modern SoC integrations and mobile systems have emphasized low power techniques due to shortage of battery life. Conventional power management designs focused on the reduction of dynamic power consumption, recent designs begin to take leakage power into consideration since it becomes an important factor in nano-scale CMOS technology. Latest development has taken advantage of modularity in SoC design methodology to develop the block-level control technique for power reductions. However, thermal gradient over the system and its impacts to SoC designs are barely discussed. In this research, a block-level optimization of comprehensive thermal aware power management is presented. The proposed design applies several low power techniques to control different power sources and handles thermal impacts to provide performance coherence. As a result, optimal powerreductions and performance coherence can be guaranteed within the whole system. The simulation results show a significant improvement in stability and leakage power reduction for most circuitries. The results are based on TSMC 100nm CMOS technology.

Mots clés: Power management designs; CMOS technology

Domaines: Architectures Matérielles [cs.AR]

W.-M. Chan, H. Chiueh. A comprehensive thermal-aware power mangement system with block-level optimization in 100nm CMOS technology. THERMINIC 2005, Sep 2005, Belgirate, Lago Maggiore, Italy. pp.7-10. ⟨hal-00189445⟩