A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS

Terje N. Andersen (1) , Atle Briskemyr (1) , Frode Telsto (1) , Johnny Bjornsen (1) , Thomas E. Bonnerud (1) , Bjornar Hernes (1) , Oystein Moldsvor (1)

1 Nordic Semiconductor, Trondheim

A 12 bit Pipeline ADC fabricated in a 0.18 µm pure digital CMOS technology is presented. Its nominal conversion rate is 110MS/s and the nominal supply voltage is 1.8V. The effective number of bits is 10.4 when a 10MHz input signal with 2V_{P-P} signal swing is applied. The occupied silicon area is 0.86mm^2 and the power consumption equals 97mW. A switched capacitor bias current circuit scale the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140MS/s.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Terje N. Andersen, Atle Briskemyr, Frode Telsto, Johnny Bjornsen, Thomas E. Bonnerud, et al.. A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18µm Digital CMOS. DATE'05, Mar 2005, Munich, Germany. pp.219-222. ⟨hal-00181852⟩