Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Takeshi Kitahara (1) , Naoyuki Kawabe (1) , Fimihiro Minami (1) , Katsuhiro Seta (1) , Toshiyuki Furusawa (2)

1 TOSHIBA Corporation Semiconductor Company
2 TOSHIBA Microelectronics Corporation

This paper presents a design flow for an improved selective multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so that plural MT-cells can share one switch transistor. We propose the design methodology from RTL(Register Transfer Level) to final layout with optimizing switch transistor structure.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Takeshi Kitahara, Naoyuki Kawabe, Fimihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa. Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. DATE'05, Mar 2005, Munich, Germany. pp.646-647. ⟨hal-00181582⟩