Tag Overflow Buffering: An Energy-Efficient Cache Architecture

Mirko Loghi (1) , Paolo Azzoni (1) , Massimo Poncino (2)

1 UNIVR | DI - Department of Computer Science [Verona]
2 Dip. di Automatica e Informatica

We propose a novel energy-efficient memory architecture which relies on the use of cache with a reduced number of tag bits. The idea behind the proposed architecture is based on moving a large number of the tag bits from the cache into an external register (Tag Overflow Buffer) that identifies the current locality of the memory references; additional hardware allows to dynamically update the value of the reference locality contained in the buffer. Energy efficiency is achieved by using, for most of the memory accesses, a reduced-tag cache. This architecture is minimally intrusive for existing designs, since it assumes the use of a regular cache, and does not require any special circuitry internal to the cache such as row or column activation mechanisms. Average energy savings are 51% on tag energy, corresponding to about 20% saving on total cache energy, measured on a set of typical embedded applications.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Mirko Loghi, Paolo Azzoni, Massimo Poncino. Tag Overflow Buffering: An Energy-Efficient Cache Architecture. DATE'05, Mar 2005, Munich, Germany. pp.520-525. ⟨hal-00181563⟩