Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

Yu-Tsun Chien (1) , Dong Chen (2) , Jea-Hong Lou (1) , Gin-Kou Ma (2) , Rob A. Rutenbar (2) , Tamal Mukherjee (2)

1 SoC Technology Center
2 ECE Dept.

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 µm CMOS process.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, et al.. Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE'05, Mar 2005, Munich, Germany. pp.279-280. ⟨hal-00181529⟩