Assertion-Based Design Exploration of DVS in Network Processor Architectures

Jia Yu (1) , Wei Wu (1) , Xi Chen (1) , Harry Hsieh (1) , Jun Yang (1) , Felice Balarin (2)

1 University of California
2 Cadence Research Laboratories

With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of network processors. In this paper, we use an assertion-based methodology for system-level power/performance analysis to study two dynamic voltage scaling (DVS) techniques, traffic-based DVS and execution-based DVS, in a network processor model. Using the automatically generated distribution analyzers, we analyze the power and performance distributions and study their trade-offs for the two DVS policies with different parameter settings such as threshold values and window sizes. We discuss the optimal configurations of the two DVS policies under different design requirements. By a set of experiments, we show that the assertion-based trace analysis methodology is an efficient tool that can help a designer easily compare and study optimal architectural configurations in a large design space.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, et al.. Assertion-Based Design Exploration of DVS in Network Processor Architectures. DATE'05, Mar 2005, Munich, Germany. pp.92-97. ⟨hal-00181501⟩