Framework for Fault Analysis and Test Generation in DRAMs

Zaid Al-Ars (1, 2, 3) , Said Hamdioui (2) , Georg Mueller (3) , Ad J. van De Goor (3)

1 CatRam Solutions
2 Lab of Computer Engineering
3 Infineon Technologies AG [München]

With the increasing complexity of memory behavior, attempts are being made to come up with a methodical approach that employs electrical simulation to tackle the memory test problem. This paper describes a framework of algorithms and tools developed jointly by the Delft University of Technology and Infineon Technologies to systematically generate DRAM tests using Spice simulation. The proposed Spice-based test approach enjoys the advantage of being relatively inexpensive, yet highly accurate in describing the desired memory faulty behavior.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Zaid Al-Ars, Said Hamdioui, Georg Mueller, Ad J. van De Goor. Framework for Fault Analysis and Test Generation in DRAMs. DATE'05, Mar 2005, Munich, Germany. pp.1020-1021. ⟨hal-00181264⟩