The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits

Irith Pomeranz (1) , Sudhakar M. Reddy (2)

1 ECE - School of Electrical and Computer Engineering [West Lafayette]
2 Electrical and Computer Eng. Dept.

We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI (f) with every circuit fault f. The heuristic estimates the number of faults that will be detected by a test generated for f. Fault ordering is done such that a fault with a higher accidental detection index appears earlier in the ordered fault set and targeted earlier during test generation. This order is effective for generating compact test sets, and for obtaining a test set with a steep fault coverage curve. Such a test set has several applications. We present experimental results to demonstrate the effectiveness of the heuristic.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Irith Pomeranz, Sudhakar M. Reddy. The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE'05, Mar 2005, Munich, Germany. pp.1008-1013. ⟨hal-00181262⟩