Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation

Kameshwar Chandrasekar (1) , Michael S. Hsiao (1)

1 ECE - Department of Electrical and Computer Engineering [Blacksburg]

In recent years, several Electronic Design Automation (EDA) problems in testing and verification have been formulated as Boolean Satisfiability (SAT) instances due to the development of efficient general-purpose SAT solvers. Problem-specific learning techniques and heuristics can be integrated into the SAT solver to further speed-up the search for a satisfying assignment. In this paper, we target the problem of generating a complete test-suite for the path delay fault (PDF) model. We provide an Incremental Satisfiability framework that learns from (1) static logic implications, (2) segment-specific clauses, and (3) unsatisfiability cores of each untestable partial PDF. These learning techniques improvise the test generation for path delay faults that have common testable and/or untestable segments. The experimental results show that a significant portion of PDFs can be excluded dynamically in the proposed incremental SAT formulation for large benchmark circuits, thus potentially achieving speed-ups for PDF test generation.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Kameshwar Chandrasekar, Michael S. Hsiao. Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. DATE'05, Mar 2005, Munich, Germany. pp.1002-1007. ⟨hal-00181261⟩