Implicit and Exact Path Delay Fault Grading in Sequential Circuits

M. M. Vaseekar Kumar (1) , S. Tragoudas (1) , S. Chakravarty (2) , R. Jayabharathi (3)

1 ECE - Department of Electrical and Computer Engineering [Carbondale]
2 Intel Corporation [Santa Clara]
3 Intel Corporation, Sacramento

The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with the support of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds on the memory requirements.

Domaines: Architectures Matérielles [cs.AR]; Electronique

M. M. Vaseekar Kumar, S. Tragoudas, S. Chakravarty, R. Jayabharathi. Implicit and Exact Path Delay Fault Grading in Sequential Circuits. DATE'05, Mar 2005, Munich, Germany. pp.990-995. ⟨hal-00181260⟩