At-Speed Logic BIST for IP Cores

B. Cheon (1) , E. Lee (1) , L.-T. Wang (2) , X. Wen (3) , P. Hsu (2) , J. Cho (4) , J. Park (4) , H. Chao (2) , S. Wu (2)

1 Samsung Electronics
2 SynTest Technologies, Inc
3 Kyutech - Kyushu Institute of Technology
4 SynTest Korea

This paper describes a flexible logic BIST scheme that features high fault coverage achieved by fault-simulation guided test point insertion, real at-speed test capability for multi-clock designs without clock frequency manipulation, and easy physical implementation due to the use of a low-speed SE signal. Application results of this scheme to two widely used IP cores are also reported.

Domaines: Architectures Matérielles [cs.AR]; Electronique

B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, et al.. At-Speed Logic BIST for IP Cores. DATE'05, Mar 2005, Munich, Germany. pp.860-861. ⟨hal-00181226⟩