Challenges in Embedded Memory Design and Test

Erik Jan Marinissen (1) , Betty Prince (2) , Doris Keitel-Schulz (3) , Yervant Zorian (4)

1 Philips Research Laboratories [Eindhoven]
2 Memory Strategies International, Leander, TX
3 Infineon Technologies AG [München]
4 Virage Logic, Fremont, CA

Both the number of embedded memories, as well as the total embedded memory content in our chips is growing steadily. Time for chip designers, EDA makers, and test engineers to update their knowledge on memories. This Hot Topic paper provides an embedded tutorial on embedded memories, in terms of what is new and coming versus what is old and vanishing, and what are the associated design, test, and repair challenges related to using embedded memories.

Domaines: Architectures Matérielles [cs.AR]; Electronique

Erik Jan Marinissen, Betty Prince, Doris Keitel-Schulz, Yervant Zorian. Challenges in Embedded Memory Design and Test. DATE'05, Mar 2005, Munich, Germany. pp.722-727. ⟨hal-00181196⟩